/*
 * Copyright (c) 2024 iSOFT INFRASTRUCTURE SOFTWARE CO., LTD.
 * easyAda is licensed under Mulan PubL v2.
 * You can use this software according to the terms and conditions of the Mulan PubL v2.
 * You may obtain a copy of Mulan PubL v2 at:
 *          http://license.coscl.org.cn/MulanPubL-2.0
 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PubL v2 for more details.
 */

#ifndef GIC_V2_H
#define GIC_V2_H
#include <stdlib/stdint.h>

/*******************************************************************************
 * CPU interface register
 ******************************************************************************/

/* CPU Interface Control Register */
#define GICC_CTLR_ENABLEGRP1_BIT   (0x1U)

/* Interrupt Acknowledge Register*/
#define GICC_IAR_ID_OFF  0U
#define GICC_IAR_ID_LEN  10U
#define GICC_IAR_CPU_OFF 10U
#define GICC_IAR_CPU_LEN 3U

/* End of Interrupt Register */
#define GICC_EOIR_ID_OFF  0U
#define GICC_EOIR_ID_LEN  10U
#define GICC_EOIR_CPU_OFF 10U
#define GICC_EOIR_CPU_LEN 3U

/* Deactivate Interrupt Register */
#define GICC_DIR_ID_OFF  0U
#define GICC_DIR_ID_LEN  10U
#define GICC_DIR_CPU_OFF 10U
#define GICC_DIR_CPU_LEN 3U

/*******************************************************************************
 * Distributor register
 ******************************************************************************/

/* Distributor Control Register, GICD_CTLR */
#define GICD_CTRL_ENABLE_OFF  1U
#define GICD_CTRL_ENABLE_MASK 1U
#define GICD_CTLR_ENABLE_BIT  (1U)

/*  Interrupt Controller Type Register, GICD_TYPER */
#define GICD_TYPER_ITLN_OFF   0U
#define GICD_TYPER_ITLN_LEN   5U
#define GICD_TYPER_CPUNUM_OFF 5U
#define GICD_TYPER_CPUNUM_LEN 3U
#define GICD_TYPER_LSPI_OFF   11U
#define GICD_TYPER_LSPI_LEN   6U

/* Software Generated Interrupt Register, GICD_SGIR */
#define GICD_SGIR_SGIINTID_OFF    0U
#define GICD_SGIR_SGIINTID_LEN    4U
#define GICD_SGIR_CPUTRGLST_OFF   16U
#define GICD_SGIR_CPUTRGLST_LEN   8U
#define GICD_SGIR_TRGLSTFLT_OFF   24U
#define GICD_SGIR_TRGLSTFLT_LEN   2U


void     gic_dist_init(uint64_t base);
void     gic_cpu_init(uint64_t base);
void     gic_send_sgi(uint32_t irq, uint32_t filter, uint8_t cpulist);
uint32_t gic_get_active_irq(void);
void     gic_enable_irq(uint32_t irq);
void     gic_disable_irq(uint32_t irq);
void     gic_set_eoi(uint32_t irq);
void     gic_set_dir(uint32_t irq);
void     gic_set_priority(uint32_t irq, uint32_t pri);
void     gic_set_cfg(uint32_t irq, uint32_t cfg);
void     gic_set_pendsgi(uint32_t irq);
void     gic_clear_pend(uint32_t irq);
void     gic_set_active(uint32_t irq);
void     gic_clear_active(uint32_t irq);
void     gic_set_targets(uint32_t irq, uint32_t target);
void     gic_set_pend(uint32_t irq);
uint32_t gic_read_typer(void);

#endif
